1. Field of the Invention
The present invention relates to a field effect transistor, an integrated circuit element, and a method for manufacturing the same.
2. Background Art
Increasing a drive current per unit gate length of each MOSFET, by reducing the gate length and thinning the gate insulating film, is a conventional general approach to enhance the performance and functionality of a CMOS circuit element. Thereby, the size of a MOSFET to provide a required drive current is reduced, which allows higher integration of MOSFETs, and a drive voltage to provide a required drive current is decreased, which reduces power consumption per unit element.
However, in recent years, technical difficulty to achieve a required high performance and functionality, by reducing the gate length and thinning the gate insulating film, has been rapidly increasing. Use of high-mobility channel material is effective to alleviate this situation. For example, strain-free SiGe (silicon germanium) and Ge (germanium) are effectively used for both of pMOS and nMOS, since these materials have higher electron mobility and hole mobility than Si (silicon). Further, compressive-strained Si, SiGe and Ge are effectively used for pMOS, since these materials have high hole mobility. Further, tensile-strained Si, SiGe and Ge are effectively used for nMOS, since these materials have high electron mobility.
Furthermore, it is possible, by using a structure having a plurality of gates, to increase the drive current while maintaining a sufficiently low off-state current. Examples of the structure include, a double-gate structure in which a gate electrode and a gate insulating film are formed on both sides of a channel, a tri-gate structure in which a gate electrode and a gate insulating film are formed on three sides (right side, left side, and upper side) of a channel, and a gate-all-around (GAA) structure in which a channel is surrounded by a gate electrode and a gate insulating film. These structures are called multi-gate structures (three-dimensional gate structures). Electrostatic force provided by their gates to control channel carriers, is larger than that provided by a typical single gate structure (planar gate structure). Therefore, in these multi-gate structures, the short channel effect can be suppressed even when the channel impurity concentration is low. In particular, an FET manufactured by, forming a plate-like protrusion (fin) on a substrate, forming a channel in the protrusion, and forming a gate electrode and a gate insulating film on both sides of the channel, is called FinFET.
Use of the high-mobility channel material and any of the multi-gate structures in combination, provides higher performance and functionality compared to using each technology alone. In fact, various kinds of preceding art using these technologies in combination, are disclosed in various preceding documents.
The preceding art can be broadly classified into three types of technologies.
The first preceding art relates to an FET formed on an SOI (Semiconductor-On-Insulator) substrate. For example, JP-A 2003-243667 (KOKAI) discloses a strained Si-FinFET manufactured by, forming a fin made of SiGe on an embedded insulating film of an SGOI (SiGe-On-Insulator) substrate, and forming strained Si around the fin. Further, JP-A 2005-159362 (KOKAI) discloses a strained Ge-FinFET manufactured by, forming a fin made of Si on an embedded insulating film of an SOI (Si-On-Insulator) substrate, and forming strained Ge around the fin. In each of these FETs, a strained layer that receives strain is formed on a core layer that induces strain, and a hetero-interface is present between the core layer and the strained layer.
The second preceding art relates to an FET formed on a bulk substrate. For example, JP-A 2005-203798 (KOKAI) discloses a multi-gate transistor manufactured by, forming a Ge layer in a predetermined region on a Si substrate by vapor epitaxial deposition, and forming a gate structure that uses the resultant facet as the channel. Further, JP-A 2005-79517 (KOKAI) discloses a multichannel-type double-gate transistor manufactured by, forming an amorphous SiGe layer in the lateral direction from the source/drain region in a Si layer by solid epitaxial deposition. In the former case, the Ge layer is formed on the Si substrate, and a hetero-interface is present between the Si substrate and the Ge layer. In the latter case, the SiGe layer is formed on the Si layer, and a hetero-interface is present between the Si layer and the SiGe layer.
The third preceding art relates to a basic technology assumed to be applied to an FET. “Tsung-Yang Liow et al., Applied Physics Letters Vol. 87, p 262104 (2005)” discloses a method for forming a high Ge composition SiGe-Fin structure on a lattice-relaxed SiGe substrate. More specifically, the document discloses a method such as, forming a lattice-relaxed SiGe layer having a thickness of about a few μm on a Si substrate, processing the SiGe layer into a fin-like shape, and performing thermal oxidization of the Si substrate, to thin the fin and increase Ge composition in the fin.
However, these kinds of preceding art have some disadvantages.
In the first and second preceding art, a hetero-interface in which Ge concentration abruptly changes across the interface, such as the hetero-interface between the Si layer and the SiGe layer and the hetero-interface between the Si layer and the Ge layer, is formed during the epitaxial deposition. Therefore, in the first and second preceding art, there is a strong possibility that lattice defects occur in a channel region or the like. The lattice defects in the channel region or the like cause problems, such as increased leak current in the transistor and reduced reliability of the transistor. In the third preceding art, oxidation-induced condensation at a low temperature of 875° C. causes insufficient interdiffusion of Si and Ge atoms, which also causes abrupt gradient of Ge concentration and the occurrence of lattice defects. Further, in “Tsung-Yang Liow et al., Applied Physics Letters Vol. 87, p 262104 (2005)” corresponding to the third art, the substrate including the Si substrate and the lattice-relaxed SiGe layer, is employed as a substrate. Since the cost for forming the thick SiGe layer by the epitaxial deposition is very high, the price of this substrate is a couple to decades of times higher than that of a typical bulk substrate. Therefore, if such a substrate is employed to manufacture transistors, the cost of the entire integrated circuit element increases greatly. In addition, the heat conductivity of SiGe is lower than that of Si by a couple of orders. Therefore, in a transistor manufactured by using such a substrate, Joule heat generated when a current passes through a channel is not dissipated sufficiently, which increases the channel temperature. As a result, characteristics of the transistor are degraded.